Cellular telephones, as with most communication systems, require high gain baseband filters within the receive signal path. In such applications, the in-band signal is amplified and conveyed to subsequent stages for processing, e.g., to an analog-to-digital converter (ADC). This analog filtering serves two purposes: reducing the magnitude of interfering signals outside the band of interest; and providing anti-aliasing.
The DC offsets in the receive signal path cause performance of the system to degrade in at least two ways. Offsets near the front end of the system get amplified by the active filter circuit and thereby reduce the available dynamic range of the ADC at the output. Additionally, offsets create errors in the two receiver signal paths commonly referred to as “in-phase” (I) and “quadrature” (Q) signal paths, thereby creating constellation distortion. Offset within the quadrature signal paths has been removed in conventional systems by using a low frequency feedback loop to cancel such offset component. In a conventional CDMA spread spectrum cellular telephone system, for example, the baseband information bandwidth extends from one to 1884 kilohertz (kHz). So as to not attenuate the low frequency baseband information, the offset cancellation loop bandwidth must be kept well below 1 kHz. So as to maintain signal integrity, low frequency phase response and group delay matching between the I and Q channels is just as important as magnitude matching. The offset cancellation loop bandwidth is typically set to approximately 100 hertz (Hz) to satisfy such requirements.
The offset compensation generally may be solved by two conventional approaches. In the first one, the offset is detected by a digital baseband processor, and a feedback signal is provided by way of a pulse density modulated (PDM) output signal generated by a modulator/demodulator (MODEM) chip. This digital signal is filtered by a first order resistive-capacitive (RC) network. The output of this filter is next fed into an analog receive filter. The drawback of such solution is that it requires external components (the RC network) for filtering the output of the PDM. Moreover, some of the baseband digital processors do not include the offset compensation feature.
The second prior art solution is based on a fully analogic feedback compensation system wherein the feedback signal is generated by way of analog integrator. As an example, U.S. Pat. No. 5,471,665 from Pace and al. discloses a differential direct current (DC) offset compensation circuit for providing DC offset compensation to a circuit device. The DC offset compensation circuit comprises a differential integrator and a summing network. The circuit device is one of several types of devices, such as a DC coupled amplifier. The differential input of the circuit device is suitable for coupling to a differential input source and the differential output of the circuit device is suitable for connection to a load. The differential integrator features a transconductance amplifier at least one other amplifier, and a capacitor element having a capacitance of C1. The summing network sums the differential integrator output with the differential input signals of the differential input source and cancels DC offsets of the differential input source and the circuit device. Such solution either implemented using a transconductance amplifier associated to capacitors or implemented using a charge pump results in excessive area and not being integrable on-chip due to the high capacitance (of the order of several nanofarad) required to obtain the low bandwidth needed.
Therefore there is a need for a fully analogic integrable offset compensation system.